1. Field of the Invention
This invention relates to field programmable gate array integrated circuit devices, and, more particularly, to improvements in field programmable gate array devices that employ antifuse programming elements that have maximum current constraints.
2. Relevant Background
In the construction of field programmable gate arrays (FPGAs), many logic modules are provided in spaced rows between sets of interconnection tracks on an integrated circuit chip. Output lines from the various logic modules extend across one or more sets of the interconnection tracks, and programmable elements are provided that can be configured by a user selectively to connect the output lines to a desired interconnection track. Corresponding connections can be made up or downstream on the track. Thus, any particular logic module can be selectively connected to any particular other logic module on the chip, as needed by the user.
The programmable elements to establish the selective connections between the output lines and the tracks can be provided by devices known in the art as "antifuses." In most antifuses, when a particular high current flows through the antifuse, it shorts to establish a permanent connection for carrying currents below a particular current level. But if a subsequent current of sufficient size passes through a completed antifuse, the integrity of the antifuse connection may be degraded, or even destroyed. This is particularly true in antifuses constructed of metal elements separated by amorphous silicon. Thus, antifuses fabricated with certain antifuse technologies may inadvertently open after being programmed. This is true even in normal circuit operations, for example, when a driver/load combination is such that a current spike rises to a level above a particular threshold. Unfortunately, for many present technologies, this current threshold is well below the level produced in normal circuit operations.
Also, in the construction of FPGAs it will be appreciated that the interconnection tracks extend considerable distances over the array, and may have a high capacitance associated with them. Additionally, the antifuses themselves are physically constructed much like capacitors, and may add to the capacitance of any particular interconnection track. As a result, despite the presence of segmenting transistors that may be provided to reduce the capacitance along the length of the interconnection tracks, a sufficiently high drive current must be applied to move a logic signal through the circuit so that the capacitive effects appearing on the line do not adversely affect the propagation time of the logic signal through the array. To provide such drive current, in the design of many gate arrays, an output driver circuit is commonly provided to receive an output logic signal from one logic module for connection to drive another logic module, or perhaps to a circuit output.
However, in view of the antifuse constraints described above, the drivers receiving the output signals from the logic modules must be reduced in size to comply with the maximum current constraint imposed by the antifuse. In turn, the propagation delays are greatly increased over those of circuits in which a sufficiently high drive current exists. Therefore, it has become necessary to introduce schemes that may meet the programmed antifuse restrictions without greatly increasing propagation delays.
The problem is sometimes further complicated by the fact that in the design of many gate arrays, designers commonly want to configure an output driver circuit to drive more than one output circuit. In such cases, because of the antifuse limitations described above, the level of the output driver current must be reduced even further not to exceed the worst case antifuse current handling limitations. For example, if an output is fanned out to include four selectable lines, the output driver must provide sufficient drive current to all four lines. Also, the output must be sufficiently low so as not to damage an antifuse structure if only one line is selected. This results in a design constraint producing undesirably slow propagation delays.
One solution proposed to solve this problem has been to provide a drive circuit that can dynamically change the output current from the drivers to provide a predetermined constant high value, despite the load or line capacitances to which it may be connected. Such amplifier designs are not particularly simple or inexpensive. When multiplied over a large array, the cost, complexity and fabrication problems of the device are greatly increased.
Examples of field programmable gate arrays in which the invention described below can be incorporated are the FPGA family of devices known as Act I or Act II, sold by Actel, Corporation, of Sunnyvale, Calif., or similar devices.